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1995 data sheet the information in this document is subject to change without notice. * description the m pd78p083 is a member of the m pd78083 subseries of the 78k/0 series products. it includes an on-chip, 24-kbyte, one-time prom or eprom. because this device can be programmed by users, it is ideally suited for applications involving the evaluation of systems in development stages, small-scale production of many different products, and rapid development and time-to-market of a new product. caution the m pd78p083du does not maintain planned reliability when used in your systems mass-produced products. please use only experimentally or for evaluation purposes during trial manufacture. the details of functions are described in the users manuals. be sure to read the following manuals before designing. m pd78083 subseries user's manual : ieu-1407 78k/0 series user's manual instructions : ieu-1372 features pin-compatible with mask rom version (except v pp pin) internal prom: 24 kbytes note ? m pd78p083du: reprogrammable (ideally suited for system evaluation) ? m pd78p083cu, m pd78p083gb: one-time programmable (ideally suited for small-scale production) internal high-speed ram: 512 bytes note can be operated in the same supply voltage as the mask rom version (v dd = 1.8 to 5.5 v) corresponding to qtop tm microcontrollers note the internal prom and internal high-speed ram capacities can be changed by setting the internal memory size switching register (ims). remark qtop microcontroller is a general term for microcontrollers which incorporate one-time prom and are totally supported by nec's programming service (from programming to marking, screening and verification). differs from the mask rom version in the following points the same memory mapping as the mask rom version is enabled by setting the internal memory size switching register (ims). in this document, the term prom is used in parts common to one-time prom versions and eprom versions. m pd78p083 mos integrated circuit 8-bit single-chip microcontroller document no. u11006ej1v0ds00 (1st edition) (previous no. ip-3556) date published june 1996 p printed in japan * the mark shows major revised points.
2 m pd78p083 ordering information part number package internal rom m pd78p083cu 42-pin plastic shrink dip (600 mil) one-time prom m pd78p083gb-3b4 44-pin plastic qfp (10 x 10 mm) one-time prom m pd78p083gb-3bs-mtx 44-pin plastic qfp (10 x 10 mm) one-time prom m pd78p083du 42-pin ceramic shrink dip eprom (with window) (600 mil) caution m pd78p083gb has two kinds of package. (refer to 9. package drawings). please refer an nec?s sales representative for the available package. quality grade part number package quality grades m pd78p083cu 42-pin plastic shrink dip (600 mil) standard m pd78p083gb-3b4 44-pin plastic qfp (10 x 10 mm) standard m pd78p083gb-3bs-mtx 44-pin plastic qfp (10 x 10 mm) standard m pd78p083du 42-pin ceramic shrink dip not applicable (with window) (600 mil) please refer to quality grades on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. *
3 m pd78p083 78k/0 series development the following shows the 78k/0 series products development. subseries names are shown inside frames. control 100-pin 100-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin fip tm drive 100-pin 80-pin 64-pin lcd drive iebus tm supported 64-pin 78k/0 series a timer was added to the pd78054 and external interface function was enhanced products in mass production products under development y subseries products are compatible with i 2 c bus. rom-less versions of the pd78078 emi noise reduced product of the pd78054 an a/d converter and 16-bit timer were added to the pd78002 an a/d converter was added to the pd78002 basic subseries for control on-chip uart, capable of operating at a low voltage (1.8 v) the i/o and fip c/d of the pd78044a were enhanced. display output total: 53 a 6-bit u/d counter was added to the pd78024. display output total: 34 basic subseries for driving fip. display output total: 26 emi noise reduced product of the pd78064 subseries for driving lcds, on-chip uart the iebus controller was added to the pd78054 on-chip pwm, lv digital code decoder, and hsync counter the enhanced sio to the pd78064 and increased rom and ram capacities low-voltage (1.8 v) operation versions of the pd78014 with several rom and ram capacities are available. uart and d/a converter were added to the pd78014 and i/o was enhanced lv control pd78078 pd78070a pd78058f pd78054 pd78018f pd78014 pd780001 pd78002 pd78083 pd78078y pd78070ay pd78058fy pd78054y pd78018fy pd78014y pd78002y pd78044a pd78024 pd780208 pd78064b pd78064 pd780308 pd78064y pd780308y pd78098 pd78p0914 80-pin 100-pin 100-pin 100-pin
4 m pd78p083 function rom timer 8-bit 8-bit serial interface i/o v dd min. external part number capacity 8-bit 16-bit watch wdt a/d d/a value expansion control m pd78078 32 k to 60 k 4ch 1ch 1ch 1ch 8ch 2ch 3ch (uart: 1ch) 88 1.8 v available m pd78070a e 61 2.7 v m pd78058f 48 k to 60 k 2ch 69 m pd78054 16 k to 60 k 2.0 v m pd78018f 8 k to 60 k e 2ch 53 1.8 v m pd78014 8 k to 32 k 2.7 v m pd780001 8 k e e 1ch 39 e m pd78002 8 k to 16 k 1ch e 53 available m pd78083 e 8ch 1ch (uart: 1ch) 33 1.8 v e fip drive m pd780208 32 k to 60 k 2ch 1ch 1ch 1ch 8ch e 2ch 74 2.7 v e m pd78044a 16 k to 40 k 68 m pd78024 24 k to 32 k 54 lcd drive m pd780308 48 k to 60 k 2ch 1ch 1ch 1ch 8ch e 3ch (uart: 1ch) 57 1.8 v e m pd78064b 32 k 2ch (uart: 1ch) 2.0 v m pd78064 16 k to 32 k iebus m pd78098 32 k to 60 k 2ch 1ch 1ch 1ch 8ch 2ch 3ch (uart: 1ch) 69 2.7 v available supported lv control m pd78p0914 32 k 6ch e e 1ch 8ch e 2ch 54 4.5 v available the following table shows the differences among subseries functions.
5 m pd78p083 function description item function internal memory prom: 24 kbytes note ram internal high-speed ram: 512 bytes note memory space 64 kbytes general register 8 bits x 32 registers (8 bits x 8 registers x 4 banks) instruction cycles instruction execution time variable function is integrated. 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (@5.0-mhz operation with main system clock) instruction set 16-bit operation multiply/divide (8 bits x 8 bits, 16 bits ? 8 bits) bit manipulation (set, reset, test, boolean operation) bcd adjust, etc. i/o ports total : 33 cmos input : 1 cmos input/output : 32 a/d converter 8-bit resolution x 8 channels serial interface 3-wire serial i/o/uart mode selectable: 1 channel timer 8-bit timer/event counter: 2 channels watchdog timer: 1 channel timer output 2 pins (8-bit pwm output enable) clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, and 5.0 mhz (@ 5.0-mhz operation with main system clock) buzzer output 1.2 khz, 2.4 khz, 4.9 khz, and 9.8 khz (@ 5.0-mhz operation with main system clock) vectored maskable interrupts internal : 8 external : 3 interrupts non-maskable interrupt internal : 1 software interrupt internal : 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = e40 to +85 c packages 42-pin plastic shrink dip (600 mil) 44-pin plastic qfp (10 x 10 mm) 42-pin ceramic shrink dip (with window) (600 mil) note internal prom and high-speed ram capacities can be changed by setting the internal memory size switching register (ims).
6 m pd78p083 pin configurations (top view) (1) normal operating mode 42-pin plastic shrink dip (600 mil) m pd78p083cu 42-pin ceramic shrink dip (with window) (600 mil) m pd78p083du cautions 1. connect v pp pin directly to v ss . 2. connect av dd pin to v dd . 3. connect av ss pin to v ss . v ss av ref p54 p53 p52 p51 p50 p100/ti5/to5 p101/ti6/to6 p70/r x d/si2 p71/t x d/so2 p72/asck/sck2 p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ss p55 av dd p56 p57 p30 p31 p32 p33 p34 p35/pcl p36/buz p37 p00 p01/intp1 p02/intp2 p03/intp3 reset v pp x2 x1 v dd 42 22 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
7 m pd78p083 44-pin plastic qfp (10 x 10 mm) m pd78p083gb-3b4, m pd78p083gb-3bs-mtx cautions 1. connect v pp pin directly to v ss . 2. connect av dd pin to v dd . 3. connect av ss pin to v ss . 4. connect nc pin to v ss for noise protection (it can be left open). p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 p72/asck/sck2 p71/t x d/so2 p70/r x d/si2 p101/ti6/to6 p100/ti5/to5 p03/intp3 p02/intp2 p01/intp1 p00 p37 p36/buz p35/pcl p34 p33 p32 nc p50 p51 p52 p53 p54 v ss p55 p56 p57 p30 p31 p11/ani1 p10/ani0 av ss av ref av dd v dd x1 x2 v pp reset nc 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34
8 m pd78p083 p00 to p03 : port 0 pcl : programmable clock p10 to p17 : port 1 buz : buzzer clock p30 to p37 : port 3 x1, x2 : crystal (main system clock) p50 to p57 : port 5 reset : reset p70 to p72 : port 7 ani0-ani7 : analog input p100, p101 : port 10 av dd : analog power supply intp1 to intp3 : interrupt from peripherals av ss : analog ground ti5, ti6 : timer input av ref : analog reference voltage to5, to6 : timer output v dd : power supply si2 : serial input v pp : programming power supply so2 : serial output v ss : ground sck2 : serial clock nc : non-connection rxd : receive data txd : transmit data asck : asynchronous serial clock
9 m pd78p083 (2) prom programming mode 42-pin plastic shrink dip (600 mil) m pd78p083cu 42-pin ceramic shrink dip (with window) (600 mil) m pd78p083du cautions 1. (l): individually connect to v ss via a pull-down resistor. 2. v ss : connect to gnd. 3. reset: set to low level. 4. open: leave open. v ss v ss a4 a3 a2 a1 a0 a10 a11 a12 a13 a14 d7 d6 d5 d4 d3 d2 d1 d0 v ss a5 v dd a6 a7 oe ce pgm a8 a9 reset v pp open v dd 42 22 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ? ? ? ? ? ? ? ? (l) (l) (l)
10 m pd78p083 44-pin plastic qfp (10 x 10 mm) m pd78p083gb-3b4, m pd78p083gb-3bs-mtx cautions 1. (l): individually connect to v ss via a pull-down resistor. 2. v ss : connect to gnd. 3. reset: set to low level. 4. open: leave open. a0 to a14 : address bus reset : reset d0 to d7 : data bus v dd : power supply ce : chip enable v pp : programming power supply oe : output enable v ss : ground pgm : program d2 d3 d4 d5 d6 d7 a14 a13 a12 a11 a10 a9 a8 (l) (l) (l) (l) (l) pgm a0 a1 a2 a3 a4 v ss a5 a6 a7 oe ce d1 d0 v ss v ss v dd v dd open v pp reset 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 ? ? ? ? ? ? ? ?
11 m pd78p083 block diagram p100/ti5/to5 p101/ti6/to6 si2/r x d/p70 so2/t x d/p71 sck2/asck/p72 ani0/p10- ani7/p17 av dd av ss av ref intp1/p01- intp3/p03 buz/p36 pcl/p35 port 0 port 1 port 3 port 5 port 7 port 10 system control 8-bit timer/ event counter 5 buzzer output interrupt control a/d converter serial interface 2 watchdog timer clock output control 8-bit timer/ event counter 6 78k/0 cpu core prom (24 kbytes) data memory (512 bytes) p00 p01-p03 p10-p17 p30-p37 p50-p57 p70-p72 p100, p101 reset x1 x2 v dd v ss v pp
12 m pd78p083 contents 1. differences between the m pd78p083 and mask rom versions 13 2. pin functions 14 2.1 pins in normal operating mode 14 2.2 pins in prom programming mode 16 2.3 pin input/output circuits and recommended connection of unused pins 16 3. internal memory size switching register (ims) 18 4. prom programming 19 4.1 operating modes 19 4.2 prom write procedure 21 4.3 prom read procedure 25 5. program erasure ( m pd78p083du only) 26 6. opaque film on erasure window ( m pd78p083du only) 26 7. one-time prom version screening 26 8. electrical specifications 27 9. package drawings 45 10. recommended soldering conditions 49 appendix a. development tools 50 appendix b. related documents 52 * *
13 m pd78p083 parameter m pd78p083 mask rom versions rom type one-time prom/eprom mask rom rom capacity 24 kbytes m pd78081 : 8 kbytes m pd78082 : 16 kbytes internal high-speed ram capacity 512 bytes m pd78081 : 256 bytes m pd78082 : 384 bytes internal rom and internal high-speed can be changed note can not be changed ram capacity change by internal memory size switching register ic pin no yes v pp pin yes no electrical specifications refer to a data sheet of each product 1. differences between the m pd78p083 and mask rom versions the m pd78p083 is a single-chip microcontroller with an on-chip one-time prom or with an on-chip eprom which has program write, erasure and rewrite capability. setting the internal memory size switching register (ims) makes the functions except the prom specification identical to the mask rom versions, that is, the m pd78081 and m pd78082. differences between the m pd78p083 and mask rom versions are shown in table 1-1. table 1-1. differences between the m pd78p083 and mask rom versions note the internal prom becomes 24 kbytes and the internal expansion ram becomes 512 bytes by the reset input.
14 m pd78p083 pin name input/output function after reset alternate function p00 input port 0 input only input ? p01 input/output 4-bit input/output port input/output is specifiable input intp1 p02 bit-wise. when used as the intp2 p03 input port, it is possible to intp3 connect a pull-up resistor by software. p10-p17 input/output port 1 input ani0-ani7 8-bit input/output port input/output is specifiable bit-wise. when used as the input port, it is possible to connect a pull-up resistor by software. note p30-p34 input/output port 3 input ? p35 8-bit input/output port pcl p36 input/output is specifiable bit-wise. buz p37 when used as the input port, it is possible to connect ? a pull-up resistor by software. p50-p57 input/output port 5 input ? 8-bit input/output port can drive up to seven leds directly. input/output is specifiable bit-wise. when used as the input port, it is possible to connect a pull-up resistor by software. p70 input/output port 7 input si2/rxd p71 3-bit input/output port so2/txd p72 input/output is specifiable bit-wise. sck2/asck when used as the input port, it is possible to connect a pull-up resistor by software. p100 input/output port 10 input ti5/to5 p101 2-bit input/output port ti6/to6 input/output is specifiable bit-wise. when used as the input port, it is possible to connect a pull-up resistor by software. 2. pin functions 2.1 pins in normal operating mode (1) port pins note when p10/ani0-p17/ani7 pins are used as the analog inputs for the a/d converter, set the port 1 to the input mode. the on-chip pull-up resistor is automatically disabled.
15 m pd78p083 (2) non-port pins pin name input/output function after reset alternate function intp1 input external interrupt input by which the active edge (rising edge, input p01 intp2 falling edge, or both rising and falling edges) can be specified. p02 intp3 p03 si2 input serial interface serial data input. input p70/rxd so2 output serial interface serial data output. input p71/txd sck2 input/output serial interface serial clock input/output. input p72/asck rxd input asynchronous serial interface serial data input. input p70/si2 txd output asynchronous serial interface serial data output. input p71/so2 asck input asynchronous serial interface serial clock input. input p72/sck2 ti5 input external count clock input to 8-bit timer (tm5). input p100/to5 ti6 external count clock input to 8-bit timer (tm6). p101/to6 to5 output 8-bit timer output. input p100/ti5 to6 p101/ti6 pcl output clock output. (for main system clock trimming) input p35 buz output buzzer output. input p36 ani0-ani7 input a/d converter analog input. input p10-p17 av ref input a/d converter reference voltage input. e e av dd e a/d converter analog power supply. connected to v dd .e e av ss e a/d converter ground potential. connected to v ss .ee reset input system reset input. e e x1 input main system clock oscillation crystal connection. e e x2 e ee v dd e positive power supply. e e v pp e high-voltage applied during program write/verification. e e connected directly to v ss in normal operating mode. v ss e ground potential. e e nc e does not internally connected. connect to v ss .ee (it can be left open)
16 m pd78p083 pin name input/output input/output recommended connection for unused pins circuit type p00 2 input connect to v ss . p01/intp1 8-a input/output independently connect to v ss via a resistor. p02/intp2 p03/intp3 p10/ani0-p17/ani7 11 input/output independently connect to v dd or v ss via p30-p32 5-a a resistor. p33, p34 8-a p35/pcl 5-a p36/buz p37 p50-p57 5-a p70/si2/rxd 8-a p71/so2/txd 5-a p72/sck2/asck 8-a p100/ti5/to5 8-a p101/ti6/to6 reset 2 input e av ref e e connect to v ss . av dd connect to v dd . av ss connect to v ss . v pp connect directly to v ss . nc connect to v ss (can leave open) 2.2 pins in prom programming mode pin name input/output function reset input prom programming mode setting when +5 v or +12.5 v is applied to the v pp pin and a low-level signal is applied to the reset pin, this chip is set in the prom programming mode. v pp input prom programming mode setting and high-voltage applied during program write/verification. a0-a14 input address bus d0-d7 input/output data bus ce input prom enable input/program pulse input oe input read strobe input to prom pgm input program/program inhibit input in prom programming mode. v dd ? positive power supply v ss ? ground potential 2.3 pin input/output circuits and recommended connection of unused pins types of input/output circuits of the pins and recommeded connection of unused pins are shown in table 2-1. for the configuration of each type of input/output circuit, see figure 2-1. table 2-1. type of input/output circuit of each pin
17 m pd78p083 figure 2-1. types of pin input/output circuits type 2 in type 8-a pull-up enable data output disable v dd p-ch n-ch p-ch in/out v dd type 11 pull-up enable data output disable v dd p-ch n-ch p-ch in/out v dd type 5-a input enable schmitt-triggered input with hysteresis characteristics pull-up enable data output disable input enable n-ch v dd p-ch in/out v dd p-ch p-ch n-ch v ref (threshold voltage) comparator + e
18 m pd78p083 3. internal memory size switching register (ims) this is a register to disable use of part of internal memories by software. by setting this internal memory size switching register (ims), it is possible to get the same memory mapping as that of the mask rom versions with a different internal memory (rom, ram). ims is set with an 8-bit memory manipulation instruction. reset input sets ims to 46h. figure 3-1. internal memory size switching register format ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 7654321 0 symbol ims address r/w fff0h 46h after reset r/w selection of internal rom3 rom2 rom1 rom0 rom capacity 00108 kbytes 010016 kbytes 011024 kbytes other than above setting prohibited table 3-1 shows the setting values of ims which make the memory mapping the same as that of the mask rom version. table 3-1. internal memory size switching register setting values ram2 ram1 ram0 selection of internal high-speed ram capacity 0 1 0 512 bytes 0 1 1 384 bytes 1 0 0 256 bytes other than above setting prohibited target mask rom versions ims setting value m pd78081 82h m pd78082 64h
19 m pd78p083 pin reset v pp v dd ce oe pgm d0 to d7 operating mode page data latch l +12.5 v +6.5 v h l h data input page write h h l high-impedance byte write l h l data input program verify l l h data output program inhibit x h h high-impedance xll read +5 v +5 v l l h data output output disable l h x high-impedance standby h x x high-impedance x : l or h 4. prom programming the m pd78p083 has an internal 24-kbyte prom as a program memory. for programming, set the prom programming mode with the v pp and reset pins. for the connection of unused pins, refer to pin configurations (top view) (2) prom programming mode. caution programs must be written in addresses 0000h to 5fffh (the last address 5fffh must be specified). they cannot be written by a prom programmer which cannot specify the write address. 4.1 operating modes when +5 v or +12.5 v is applied to the v pp pin and a low-level signal is applied to the reset pin, the prom programming mode is set. this mode will become the operating mode as shown in table 4-1 when the ce, oe, and pgm pins are set as shown. further, when the read mode is set, it is possible to read the contents of the prom. table 4-1. operating modes of prom programming
20 m pd78p083 (1) read mode read mode is set if ce = l, oe = l is set. (2) output disable mode data output becomes high-impedance, and is in the output disable mode, if oe = h is set. therefore, it allows data to be read from any device by controlling the oe pin, if multiple m pd78p083s are connected to the data bus. (3) standby mode standby mode is set if ce = h is set. in this mode, data outputs become high-impedance irrespective of the oe status. (4) page data latch mode page data latch mode is set if ce = h, pgm = h, oe = l are set at the beginning of page write mode. in this mode, 1 page 4-byte data is latched in an internal address/data latch circuit. (5) page write mode after 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active low) to the pgm pin with ce = h, oe = h. then, program verification can be performed, if ce = l, oe = l are set. if programming is not performed by a one-time program pulse, x times (x 10) write and verification operations should be executed repeatedly. (6) byte write mode byte write is executed when a 0.1-ms program pulse (active low) is applied to the pgm pin with ce = l, oe = h. then, program verification can be performed if oe = l is set. if programming is not performed by a one-time program pulse, x times (x 10) write and verification operations should be executed repeatedly. (7) program verify mode program verify mode is set if ce = l, pgm = h, oe = l are set. in this mode, check if a write operation is performed correctly after the write. (8) program inhibit mode program inhibit mode is used when the oe pin, v pp pin, and d0-d7 pins of multiple m pd78p083s are connected in parallel and a write is performed to one of those devices. when a write operation is performed, the page write mode or byte write mode described above is used. at this time, a write is not performed to a device which has the pgm pin driven high.
21 m pd78p083 4.2 prom write procedure figure 4-1. page program mode flow chart g = start address n = program last address start address = g v dd = +6.5 v, v pp = +12.5 v x = 0 latch address = address + 1 latch address = address + 1 latch address = address + 1 latch x = x + 1 x = 10 ? address = n ? v dd = 4.5 to 5.5 v, v pp = v dd yes no fail fail all pass pass no yes pass address = address + 1 0.1-ms program pulse verify 4 bytes verify all bytes write end defective product
22 m pd78p083 figure 4-2. page program mode timing a2-a14 a0, a1 d0-d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il page data latch page program program verify data output data input
23 m pd78p083 figure 4-3. byte program mode flow chart g = start address n = program last address start address = g v dd = +6.5 v, v pp = +12.5 v x = 0 x = x + 1 address = n ? v dd = 4.5 to 5.5 v, v pp = v dd yes no fail fail all pass pass no yes pass address = address + 1 x = 10 ? 0.1-ms program pulse verify verify all bytes write end defective product
24 m pd78p083 figure 4-4. byte program mode timing cautions 1. v dd should be applied before v pp and removed after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. reliability may be adversely affected if removal/reinsertion is performed while +12.5 v is being applied to v pp . program data input data output program verify a0-a14 d0-d7 v pp v pp v dd v dd + 1.5 v dd v ih v il v dd ce v ih v il pgm v ih v il oe
25 m pd78p083 a0-a14 ce (input) oe (input) d0-d7 hi-z address input data output hi-z 4.3 prom read procedure the contents of prom are readable to the external data bus (d0-d7) according to the read procedure shown below. (1) fix the reset pin at low level, supply +5 v to the v pp pin, and connect all other unused pins as shown in pin configurations (top view) (2) prom programming mode. (2) supply +5 v to the v dd and v pp pins. (3) input address of read data into the a0-a16 pins. (4) read mode (5) output data to d0-d7 pins. the timings of the above steps (2) to (5) are shown in figure 4-5. figure 4-5. prom read timings
26 m pd78p083 5. program erasure ( m pd78p083du only) the m pd78p083du is capable of erasing (ffh) the data written in a program memory and rewriting. to erase the programmed data, expose the erasure window to light having a wavelength shorter than about 400 nm. normally, irradiate ultraviolet rays of 254-nm wavelength. the amount of exposure required to completely erase the programmed data is as follows: uv intensity x erasing time : 30 w s/cm 2 or more erasure time: 40 min. or more (when a uv lamp of 12,000 m w/cm 2 is used. however, a longer time may be needed because of deterioration in performance of the uv lamp, soiled erasure window, etc.) when erasing the contents of data, set up the uv lamp within 2.5 cm from the erasure window. further, if a filter is provided for a uv lamp, irradiate the ultraviolet rays after removing the filter. 6. opaque film on erasure window ( m pd78p083du only) to protect from unintentional erasure by rays other than that of the lamp for erasing eprom contents, or to protect internal circuit other than eprom from misoperating by rays, cover the erasure window with an opaque film when eprom contents erasure is not performed. 7. one-time prom version screening the one-time prom version ( m pd78p083cu, 78p083gb-3b4, 78p083gb-3bs-mtx) cannot be tested completely by nec before it is shipped, because of its structure. it is recommended to perform screening to verify prom after writing necessary data and performing high-temperature storage under the condition below. storage temperature storage time 125 c 24 hours nec offers for an additional fee one-time prom writing to marking, screening, and verify for products designated as "qtop microcontroller". please contact an nec sales representative for details. * *
27 m pd78p083 parameter symbol test conditions ratings unit supply voltage v dd e0.3 to +7.0 v v pp e0.3 to +13.5 v av dd e0.3 to v dd + 0.3 v av ref e0.3 to v dd + 0.3 v av ss e0.3 to +0.3 v input voltage v i1 e0.3 to v dd + 0.3 v v i2 a9 prom programming mode e0.3 to +13.5 v output voltage v o e0.3 to v dd + 0.3 v analog input voltage v an p10-p17 analog input pins av ss e 0.3 to av ref + 0.3 v output current, high i oh per pin e10 ma total for p10-p17, p50-p54, p70-p72, e15 ma p100, p101 total for p01-p03, p30-p37, p55-p57 e15 ma output current, low i ol note per pin peak value 30 ma r.m.s. value 15 ma total for p50-p54 peak value 100 ma r.m.s. value 70 ma total for p55-p57 peak value 100 ma r.m.s. value 70 ma total for p10-p17, p70-p72, p100, peak value 50 ma p101 r.m.s. value 20 ma total for p01-p03, p30-p37 peak value 50 ma r.m.s. value 20 ma operating ambient temperature t a e40 to +85 c storage temperature t stg e65 to +150 c 8. electrical specifications absolute maximum ratings (t a = 25 c) * note the r.m.s. value should be calculated as follows: [r.m.s. value] = [peak value] x duty caution if the absolute maximum rating of even one of the above parameters is exceeded, the quality of the product may be degraded. the absolute maximum ratings are therefore the rated values that may, if exceeded, physically damage the product. be sure to use the product with all the absolute maximum ratings observed. remark unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.
28 m pd78p083 resonator recommended parameter test conditions min. typ. max. unit circuit ceramic oscillation frequency v dd = oscillation voltage 1.0 5.0 mhz resonator (f x ) note 1 range oscillation stabilization after v dd came to min. 4 ms time note 2 of oscillation voltage range crystal oscillation frequency 1.0 5.0 mhz resonator (f x ) note 1 oscillation stabilization v dd = 4.5 to 5.5 v 10 ms time note 2 30 external clock x1 input frequency 1.0 5.0 mhz (f x ) note 1 x1 input high- and 85 500 ns low-level widths (t xh , t xl ) parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz, unmeasured pins returned to 0 v. 15 pf i/o capacitance c io f = 1 mhz, p01-p03, p10-p17, p30-p37, 15 pf unmeasured pins p50-p57, p70-p72, p100, returned to 0 v. p101 capacitance (t a = 25 c, v dd = v ss = 0 v) remark unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics. main system clock oscillator characteristics (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. only the oscillator characteristics are shown. for the instruction execution time, refer to ac characteristics . 2. time required for oscillation to stabilize after a reset or the stop mode has been released. caution when using the oscillation circuit of the main system clock, wire the portion enclosed in broken lines in the figures as follows to avoid adverse influences on the wiring capacitance: keep the wiring length as short as possible. do not cross the wiring over other signal lines. do not route the wiring in the vicinity of lines through which a high fluctuating current flows. always keep the ground point of the capacitor of the oscillation circuit at the same potential as v ss . do not connect the power source pattern through which a high current flows. do not extract signals from the oscillation circuit. v pp c1 x1 c2 x2 v pp c1 x1 c2 x2 x2 x1 pd74hcu04 m
29 m pd78p083 dc characteristics (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) remark unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics. 0.8v dd 0.85v dd 0 0.2v dd 0 0.15v dd v dd v v dd v v v parameter symbol test conditions min. typ. max. unit input voltage, high v ih1 p10-p17, p30-p32, v dd = 2.7 to 5.5 v 0.7v dd v dd v p35-p37, p50-p57, p71 v ih2 p00-p03, p33, p34, v dd = 2.7 to 5.5 v 0.8v dd v dd v p70, p72, p100, p101, reset v ih3 x1, x2 v dd = 2.7 to 5.5 v v dd e0.5 v dd v v dd e0.2 v dd v input voltage, low v il1 p10-p17, p30-p32, v dd = 2.7 to 5.5 v 0 0.3v dd v p35-p37, p50-p57, p71 v il2 p00-p03, p33, p34, v dd = 2.7 to 5.5 v 0 0.2v dd v p70, p72, p100, p101, reset v il3 x1, x2 v dd = 2.7 to 5.5 v 0 0.4 v 0 0.2 v output voltage, high v oh v dd = 4.5 to 5.5 v, i oh = e1 ma v dd e1.0 v i oh = e100 m av dd e0.5 v output voltage, low v ol p50-p57 v dd = 2.0 to 4.5 v, 0.8 v i ol = 10 ma v dd = 4.5 to 5.5 v, 0.4 2.0 v i ol = 15 ma p01-p03, p10-p17, v dd = 4.5 to 5.5 v, 0.4 v p30-p37, p70-p72, i ol = 1.6 ma p100, p101 i ol = 400 m a 0.5 v input-leak current, high i lih1 v in = v dd p00-p03, p10-p17, 3 m a p30-p37, p50-p57, p70-p72, p100, p101, reset i lih2 x1, x2 20 m a input-leak current, low i lil1 v in = 0 v p00-p03, p10-p17, e3 m a p30-p37, p50-p57, p70-p72, p100, p101, reset i lil2 x1, x2 e20 m a output leak current, high i loh v out = v dd 3 m a output leak current, low i lol v out = 0 v e3 m a software pull-up resistor r v in = 0 v p01-p03, p10-p17, 15 40 90 k w p30-p37, p50-p57, p70-p72, p100, p101
30 m pd78p083 parameter symbol test conditions min. typ. max. unit supply current note 1 i dd1 5.0-mhz crystal v dd = 5.0 v 10% note 4 5.4 16.2 ma oscillation operating v dd = 3.0 v 10% note 5 0.8 2.4 ma mode (f xx = 2.5 mhz) note 2 v dd = 2.0 v 10% note 5 0.45 1.35 ma 5.0-mhz crystal oscil- v dd = 5.0 v 10% note 4 9.5 28.5 ma lation operating mode v dd = 3.0 v 10% note 5 1.0 3.0 ma (f xx = 5.0 mhz) note 3 i dd2 5.0-mhz crystal oscil- v dd = 5.0 v 10% 1.4 4.2 ma lation halt mode v dd = 3.0 v 10% 0.5 1.5 ma (f xx = 2.5 mhz) note 2 v dd = 2.0 v 10% 280 840 m a 5.0-mhz crystal oscil- v dd = 5.0 v 10% 1.6 4.8 ma lation halt mode v dd = 3.0 v 10% 0.65 1.95 ma (f xx = 5.0 mhz) note 3 i dd3 stop mode v dd = 5.0 v 10% 0.1 30 m a v dd = 3.0 v 10% 0.05 10 m a v dd = 2.0 v 10% 0.05 10 m a dc characteristics (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. not including av ref , av dd currents or port currents (including current flowing into internal pull-up resistors). 2. f xx = f x /2 operation (when oscillation mode selection register (osms) is set to 00h). 3. f xx = f x operation (when oscillation mode selection register (osms) is set to 01h). 4. high-speed mode operation (when processor clock control register (pcc) is set to 00h). 5. low-speed mode operation (when processor clock control register (pcc) is set to 04h). remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency
31 m pd78p083 ac characteristics (1) basic operation (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit cycle time t cy f xx = f x /2 note1 v dd = 2.7 to 5.5 v 0.8 64 m s (minimum instruction execution 2.0 64 m s time) f xx = f x note2 3.5 v v dd 5.5 v 0.4 32 m s 2.7 v v dd < 3.5 v 0.8 32 m s ti5, ti6 f ti v dd = 4.5 to 5.5 v 0 4 mhz input frequency 0 275 khz ti5, ti6 input high-/ t tih ,v dd = 4.5 to 5.5 v 100 ns low-level widths t til 1.8 m s interrupt input high-/ t inth ,v dd = 2.7 to 5.5 v 10 m s low-level widths t intl 20 m s reset low-level width t rsl v dd = 2.7 to 5.5 v 10 m s 20 m s notes 1. when oscillation mode selection register (osms) is set to 00h. 2. when osms is set to 01h. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency t cy vs v dd t cy vs v dd (main system clock f xx = f x /2 operation) (main system clock f xx = f x operation) 60 10 2.0 1.0 0.5 0.4 0 123456 power supply voltage v dd [v] cycle time t cy [ s] m operation guaranteed range 60 10 2.0 1.0 0.5 0.4 0 123456 power supply voltage v dd [v] cycle time t cy [ s] m operation guaranteed range
32 m pd78p083 (2) serial interface (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (sck2 internal clock output) note c is the sck2, so2 output line load capacitance. (b) 3-wire serial i/o mode (sck2 external clock input) parameter symbol test conditions min. typ. max. unit sck2 cycle time t kcy1 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck2 high-/low-level width t kh1 ,v dd = 4.5 to 5.5 v t kcy1 /2e50 ns t kl1 t kcy1 /2e100 ns si2 setup time t sik1 4.5 v v dd 5.5 v 100 ns (to sck2 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si2 hold time t ksi1 400 ns (from sck2 - ) sck2 ? so2 t kso1 c = 100 pf note 300 ns output delay time parameter symbol test conditions min. typ. max. unit sck2 cycle time t kcy2 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck2 high-/low-level width t kh2 , 4.5 v v dd 5.5 v 400 ns t kl2 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns si2 setup time t sik2 v dd = 2.0 to 5.5 v 100 ns (to sck2 - ) 150 ns si2 hold time t ksi2 400 ns (from sck2 - ) sck2 ? so2 t kso2 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns output delay time 500 ns sck2 rise, fall time t r2 , 1000 ns t f2 note c is the so2 output line load capacitance.
33 m pd78p083 (c) uart mode (dedicated baud rate generator output) parameter symbol test conditions min. typ. max. unit transfer rate 4.5 v v dd 5.5 v 78125 bps 2.7 v v dd < 4.5 v 39063 bps 2.0 v v dd < 2.7 v 19531 bps 9766 bps parameter symbol test conditions min. typ. max. unit asck cycle time t kcy3 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns asck high-/low-level width t kh3 , 4.5 v v dd 5.5 v 400 ns t kl3 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns transfer rate 4.5 v v dd 5.5 v 39063 bps 2.7 v v dd < 4.5 v 19531 bps 2.0 v v dd < 2.7 v 9766 bps 6510 bps asck rise, fall time t r3 , 1000 ns t f3 (d) uart mode (external clock input)
34 m pd78p083 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points ac timing test point (excluding x1 input) clock timing ti timing 1/f ti t til t tih ti5, ti6 1/f x t xl t xh v dd e 0.5 v 0.4 v x1 input
35 m pd78p083 serial transfer timing 3-wire serial i/o mode: t kso1, 2 sck2 si2 so2 input data output data t kcy1, 2 t kh1, 2 t kl1, 2 t sik1, 2 t ksi1, 2 t r2 t f2 uart mode (external clock input): asck t kl3 t kh3 t r3 t f3 t kcy3
36 m pd78p083 a/d converter characteristics (t a = e40 to +85 c, av dd = v dd = 2.7 to 5.5 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit resolution 888bit total error note 2.7 v av ref av dd 1.4 % conversion time t conv 19.1 200 m s sampling time t samp 12/f xx m s analog input voltage v ian av ss av ref v reference voltage av ref 2.7 av dd v av ref -av ss resistance r airef 414 k w note excluding quantization error ( 1/2 lsb). shown as a percentage of the full scale value. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency
37 m pd78p083 parameter symbol test conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v data retention supply current i dddr v dddr = 1.8 v 0.1 10 m a release signal set time t srel 0 m s oscillation stabilization wait t wait release by reset 2 17 /f x ms time release by interrupt note ms data memory stop mode low supply voltage data retention characteristics (t a = e40 to +85 c) note 2 12 /f xx or 2 14 /f xx -2 17 /f xx can be selected by bit 0-bit 2 (osts0-osts2) of oscillation stabilization time selection register (osts). remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode released by reset) data retention timing (standby release signal: stop mode released by interrupt signal) stop instruction execution v dd v dddr operating mode halt mode stop mode data retention mode t wait reset t srel internal reset operation stop instruction execution v dd v dddr standby release signal (interrupt request) operating mode halt mode stop mode data retention mode t wait t srel
38 m pd78p083 interrupt input timing reset input timing intp1-intp3 t intl t inth reset t rsl
39 m pd78p083 prom programming characteristics dc characteristics ( 1) prom write mode (t a = 25 5?c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) parameter symbol symbo l note test conditions min. typ. max. unit input voltage, high v ih v ih 0.7v dd v dd v input voltage, low v il v il 0 0.3v dd v output voltage, high v oh v oh i oh = e1 ma v dd e 1.0 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 v in v dd e10 +10 m a v pp supply voltage v pp v pp 12.2 12.5 12.8 v v dd supply voltage v dd v cc 6.25 6.5 6.75 v v pp supply current i pp i pp pgm = v il 50 ma v dd supply current i dd i cc 50 ma (2) prom read mode (t a = 25 5?c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) parameter symbol symbo l note test conditions min. typ. max. unit input voltage, high v ih v ih 0.7v dd v dd v input voltage, low v il v il 0 0.3v dd v output voltage, high v oh1 v oh1 i oh = e1 ma v dd e 1.0 v v oh2 v oh2 i oh = e100 m av dd e 0.5 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 v in v dd e10 +10 m a output leakage current i lo i lo 0 v out v dd , oe = v ih e10 +10 m a v pp supply voltage v pp v pp v dd e 0.6 v dd v dd + 0.6 v v dd supply voltage v dd v cc 4.5 5.0 5.5 v v pp supply current i pp i pp v pp = v dd 100 m a v dd supply current i dd i cca1 ce = v il , v in = v ih 50 ma note corresponding m pd27c1001a symbol.
40 m pd78p083 parameter symbol symbo l note test conditions min. typ. max. unit address setup time (to pgm )t as t as 2 m s oe set time t oes t oes 2 m s ce setup time (to pgm )t ces t ces 2 m s input data setup time (to pgm )t ds t ds 2 m s address hold time (from oe - )t ah t ah 2 m s input data hold time t dh t dh 2 m s (from pgm - ) oe - ? data output float t df t df 0 250 ns delay time v pp setup time (to pgm )t vps t vps 1.0 ms v dd setup time (to pgm )t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms oe ? valid data delay time t oe t oe 1 m s oe hold time t oeh ?2 m s parameter symbol symbo l note test conditions min. typ. max. unit address setup time (to oe )t as t as 2 m s oe setup time t oes t oes 2 m s ce setup time (to oe )t ces t ces 2 m s input data setup time (to oe )t ds t ds 2 m s address hold time (from oe - )t ah t ah 2 m s t ahl t ahl 2 m s t ahv t ahv 0 m s input data hold time (from oe - )t dh t dh 2 m s oe - ? data output float t df t df 0 250 ns delay time v pp setup time (to oe )t vps t vps 1.0 ms v dd setup time (to oe )t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms oe ? valid data delay time t oe t oe 1 m s oe pulse width during data t lw t lw 1 m s latching pgm setup time t pgms t pgms 2 m s ce hold time t ceh t ceh 2 m s oe hold time t oeh t oeh 2 m s ac characteristics (1) prom write mode (a) page program mode (t a = 25 5?c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) (b) byte program mode (t a = 25 5?c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) note corresponding m pd27c1001a symbol.
41 m pd78p083 (2) prom read mode (t a = 25 5?c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) parameter symbol symbo l note test conditions min. typ. max. unit address ? data output t acc t acc ce = oe = v il 800 ns delay time ce ? data output delay time t ce t ce oe = v il 800 ns oe ? data output delay time t oe t oe ce = v il 200 ns oe - ? data output float t df t df ce = v il 060ns delay time address ? data hold time t oh t oh ce = oe = v il 0ns parameter symbol test conditions min. typ. max. unit prom programming mode t sma 10 m s setup time note corresponding m pd27c1001a symbol. (3) prom programming mode (t a = 25?c, v ss = 0 v)
42 m pd78p083 prom write mode timing (page program mode) a2-a14 a0, a1 d0-d7 v pp v dd v pp v dd +1.5 v dd v dd v ih v il ce v ih v il pgm v ih v il oe t lw t pw t ceh t as t ds t vps t vds hi-z hi-z data input t pgms t dh t ahl t ahv t df t oe data output t ah hi-z t ces t oeh t oes page data latch page program program verify
43 m pd78p083 notes 1. if you want to read within the range of t acc , make the oe input delay time from the fall of ce a maximum of t acc e t oe . 2. t df is the time from when either oe or ce first reaches v ih . prom write mode timing (byte program mode) cautions 1. v dd should be applied before v pp , and removed after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. reliability may be adversely affected if removal/reinsertion is performed while + 12.5 v is being applied to v pp . prom read mode timing a0-a14 v ih ce v il v ih oe v il d0-d7 data output effective address hi-z hi-z t ce t acc note 1 t df note 2 t oh t oe note 1 a0-a14 v pp d0-d7 v pp v dd v dd +1.5 v dd v dd v ih ce v il v ih pgm v il v ih oe v il t vps t as t ds t vds t ces t pw t oes t oe t oeh t dh hi-z hi-z hi-z t df t ah program verify program data input data output
44 m pd78p083 prom programming mode setting timing t sma effective address v dd 0 v dd v dd 0 v pp reset a0-a14
45 m pd78p083 9. package drawings 42pin plastic shrink dip (600 mil) item millimeters inches a b c f g h i j k 39.13 max. 1.778 (t.p.) 3.20.3 0.51 min. 4.31 max. 1.78 max. 0.17 15.24 (t.p.) 5.08 max. n 0.9 min. r 1.541 max. 0.070 max. 0.035 min. 0.1260.012 0.020 min. 0.170 max. 0.200 max. 0.600 (t.p.) 0.007 0.070 (t.p.) p42c-70-600a-1 a c d g notes 1) each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. d 0.500.10 0.020 m 0.25 0.010 +0.10 e0.05 0~15? 0~15? +0.004 e0.003 +0.004 e0.005 m k n l 13.2 0.520 2) item "k" to center of leads when formed parallel. 42 1 22 21 l m r b f h j i remark the shape and material of es versions are the same as those of mass-produced versions.
46 m pd78p083 m pd78p083gb-3b4 44 pin plastic qfp ( 10) note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. p44gb-80-3b4-3 item millimeters inches a b c 13.60.4 10.00.2 10.00.2 0.535 0.394 0.394 d 13.60.4 0.535 f 1.0 0.039 g 1.0 0.039 h 0.350.10 0.014 i 0.15 0.006 j 0.8 (t.p.) 0.031 (t.p) k 1.80.2 0.071 l 0.80.2 0.031 m 0.15 0.006 n 0.10 0.004 p 2.7 0.106 q 0.10.1 0.0040.004 r 5?5? 5?5? s 3.0 max. 0.119 max. +0.017 e0.016 +0.008 e0.009 +0.008 e0.009 +0.017 e0.016 +0.004 e0.005 +0.008 e0.009 +0.009 e0.008 +0.004 e0.003 n l detail of lead end g m i j h a f m q r b 33 34 22 44 1 12 11 23 c d s p k +0.10 e0.05 remark the shape and material of es versions are the same as those of mass-produced versions.
47 m pd78p083 m pd78p083gb-3bs-mtx 44 pin plastic qfp ( 10) s44gb-80-3bs item millimeters inches n p q 0.1250.075 0.10 2.7 0.004 0.106 0.0050.003 note each lead centerline is located within 0.16 mm (0.007 inch) of its true position (t.p.) at maximum material condition. j i h n a 13.20.2 0.520 +0.008 e0.009 b 10.00.2 0.394 +0.008 e0.009 c 10.00.2 0.394 +0.008 e0.009 d 13.20.2 0.520 +0.008 e0.009 f g h 1.0 0.37 1.0 0.039 0.039 0.015 +0.003 e0.004 i j k 0.8 (t.p.) 1.60.2 0.16 0.007 0.031 (t.p.) 0.0630.008 l 0.80.2 0.031 +0.009 e0.008 m 0.17 0.007 +0.002 e0.003 s 3.0 max. 0.119 max. r3 3 +7 e3 +0.08 e0.07 +0.06 e0.05 +7 e3 detail of lead end q f g k m l r m 33 34 22 44 1 12 11 23 s p cd a b remark the shape and material of es versions are the same as those of mass-produced versions.
48 m pd78p083 x 42 22 121 y a z d f 0?15 k j 42pin ceramic shrink dip (window) (600 mil) g i h m n c b m p42dw-70-600a item millimeters inches a b c d f g h i j k l 38.25 max. 1.778 (t.p.) 0.46 0.05 0.85 min. 3.5 0.3 1.02 min. 3.026 1.345 max. 1.506 max. 0.033 min. 0.138 0.012 0.119 0.208 max. 0.053 max. notes m n x 12.0 0.25 0.25 0.05 14.99 15.24 (t.p.) 5.282 max. 0.018 0.002 0.01 0.472 0.010 +0.002 ?.003 0.590 1) each lead centerline is located within 0.25 mm (0.01 inch) of its true position (t.p.) at maximum material condition. 0.600 (t.p.) 0.040 min. y z 4-r3.0 6.0 0.236 4-r0.118 0.07 (t.p.) 2) item "k" to center of leads when formed parallel. l
49 m pd78p083 10. recommended soldering conditions it is recommended that the m pd78p083 be soldered under the following conditions. for details on the recommended soldering conditions, refer to information document "semiconductor device mounting technology manual" (c10535e) . for soldering methods and conditions other than those recommended, please contact your nec sales representative. table 10-1. soldering conditions for surface mount types m pd78p083gb-3b4 : 44-pin plastic qfp (10 x 10 mm) m pd78p083gb-3bs-mtx : 44-pin plastic qfp (10 x 10 mm) caution do not use different soldering methods together (except for partial heating method). table 10-2. soldering condition for hole-through types m pd78p083cu : 42-pin plastic shrink dip (600 mil) m pd78p083du : 42-pin ceramic shrink dip (with window) (600 mil) soldering method soldering conditions wave soldering solder temperature: 260 c or below, flow time: 10 seconds or less (only pins) partial heating pin temperature: 300 c or below, flow time: 3 seconds or less (per pin) soldering method soldering conditions symbol infrared ray reflow package peak temperature: 235?c, reflow time: 30 seconds or ir35-00-2 less (at 210?c or higher), number of reflow processes: 2 or less < cautions > (1) wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) do not perform flux cleaning with water after the first reflow. vps package peak temperature: 215?c, reflow time: 40 seconds or vp15-00-2 less (at 200?c or higher), number of reflow processes: 2 or less < cautions > (1) wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) do not perform flux cleaning with water after the first reflow. wave soldering solder temperature: 260?c or below, flow time: 10 seconds or ws60-00-1 less, number of flow processes: 1, preheating temperature: 120?c max. (package surface temperature) partial heating pin temperature: 300?c or below, ? flow time: 3 seconds or less (per pin row) * caution apply wave soldering only to the pins and be careful so as not to bring solder into direct contact with the package.
m pd78p083 50 * appendix a. development tools the following development tools are available to support development of systems using the m pd78p083. language processing software ra78k/0 notes 1, 2, 3, 4 assembler package common to the 78k/0 series cc78k/0 notes 1, 2, 3, 4 c compiler package common to the 78k/0 series df78083 notes 1, 2, 3, 4 device file used for the m pd78083 subseries cc78k/0el notes 1, 2, 3, 4 c compiler library source file common to the 78k/0 series prom writing tools pg-1500 prom programmer pa-78p083cu programmer adapter connected to the pg-1500 pa-78p083gb pg-1500 controller notes 1, 2 control program for the pg-1500 debugging tools ie-78000-r in-circuit emulator common to the 78k/0 series ie-78000-r-a note 8 in-circuit emulator common to the 78k/0 series (for integrated debugger) ie-78000-r-bk break board common to the 78k/0 series ie-78078-r-em emulation board common to the m pd78078 subseries ep-78083cu-r emulation probe for the m pd78083 subseries ep-78083gb-r ev-9200g-44 socket mounted on the target system board prepared for 44-pin plastic qfp sm78k0 notes 5, 6, 7 system simulator common to the 78k/0 series id78k0 notes 4, 5, 6, 7, 8 integrated debugger for ie-78000-r-a sd78k/0 notes 1, 2 screen debugger for the ie-78000-r df78083 notes 1, 2, 5, 6, 7 device file used for the m pd78083 subseries notes 1. based on pc-9800 series (ms-dos tm ) 2. based on ibm pc/at tm and its compatibles (pc dos tm /ibm dos tm /ms-dos) 3. based on hp9000 series 300 tm (hp-ux tm ) 4. based on hp9000 series 700 tm (hp-ux), sparcstation tm (sunos tm ), and ews4800 series (ews-ux/v) 5. based on pc-9800 series (ms-dos + windows tm ) 6. ibm pc/at and its compatibles (pc dos/ibm dos/ms-dos + windows) 7. based on news tm (news-os tm ) 8. under development remarks 1. please refer to the 78k/0 series selection guide (u11126e) for information on the third party development tools. 2. use the ra78k/0, cc78k/0, sm78k0, id78k0, and sd78k/0 in combination with the df78083.
m pd78p083 51 fuzzy inference development support system fe9000 note 1 /fe9200 note 2 fuzzy knowledge data creation tool ft9080 note 1 /ft9085 note 3 translator fi78k0 notes 1, 3 fuzzy inference module fd78k0 notes 1, 3 fuzzy inference debugger notes 1. based on pc-9800 series (ms-dos) 2. based on ibm pc/at and its compatibles (pc dos/ibm dos/ms-dos+windows) 3. based on ibm pc/at and its compatibles (pc dos/ibm dos/ms-dos) remark please refer to the 78k/0 series selection guide (u11126e) for information on the third party development tools.
m pd78p083 52 appendix b. related documents documents related to devices document name document no. japanese english m pd78083 subseries user?s manual ieu-886 ieu-1407 78k/0 series user?s manual?instructions ieu-849 ieu-1372 78k/0 series instruction table u10903j ? 78k/0 series instruction set u10904j ? m pd78083 subseries special function register table iem-5599 ? 78k/0 series application note basic (iii) iea-767 u10182e documents related to development tools (user's manual) document name document no. japanese english ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k/0 c compiler application note programming eea-618 eea-1208 know-how cc78k series library source file eeu-777 ? pg-1500 prom programmer eeu-651 eeu-1335 pg-1500 controller pc-9800 series (ms-dos) based eeu-704 eeu-1291 pg-1500 controller ibm pc series (pc dos) based eeu-5008 u10540e ie-78000-r eeu-810 eeu-1398 ie-78000-r-a u10057j u10057e ie-78000-r-bk eeu-867 eeu-1427 ie-78078-r-em u10775j eeu-1504 ep-78083 eeu-5003 eeu-1529 sm78k0 system simulator reference eeu-5002 u10181e sm78k series system simulator third party?s user u10092j u10092e open interface specifications sd78k/0 screen debugger introduction eeu-852 ? pc-9800 series (ms-dos) based reference u10952j ? sd78k/0 screen debugger introduction eeu-5024 eeu-1414 ibm pc/at (pc dos) based reference eeu-993 eeu-1413 caution the contents of the documents listed above are subject to change without prior notice. make sure to use the latest edition when starting design. *
m pd78p083 53 documents related to embedded software (user?s manual) document name document no. japanese english 78k/0 series os mx78k0 basic eeu-5010 ? fuzzy knowledge data creation tool eeu-829 eeu-1438 78k/0, 78k/ii, and 87ad series fuzzy inference development support system translator eeu-862 eeu-1444 78k/0 series fuzzy inference development support system fuzzy inference module eeu-858 eeu-1441 78k/0 series fuzzy inference development support system fuzzy inference debugger eeu-921 eeu-1458 other documents document name document no. japanese english semiconductor device package manual iei-635 iei-1213 semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices iei-620 iei-1209 nec semiconductor device reliability/quality control system c10983j c10983e electrostatic discharge (esd) test mem-539 iei-1201 guide to quality assurance for semicoductor devices mei-603 mei-1202 microcontroller-related product guide e third party products e mei-604 ? caution the contents of the documents listed above are subject to change without prior notice. be sure to use the latest edition when starting design.
m pd78p083 54 [memo]
m pd78p083 55 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and trans- ported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. fip, iebus, and qtop are trademarks of nec corporation. ms-dos and windows are trademarks of microsoft corporation. ibm dos, pc/at and pc dos are trademarks of international business machines corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation.
m pd78p083 the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representive. license not needed : m pd78p083du the customer must judge the need for license : m pd78p083cu, 78p083gb-3b4, 78p083gb-3bs-mtx m4 94.11 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product.

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